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Free Training About Formal Verification in IC Design
 

Invitation for the seminar

 

Nowadays, hardware designs can contain up to several hundred million transistors. Providing a high integrity circuit with such a design requires a careful argument for its justification. Moreover, with the increasing complexity of circuits, a significant part of the design efforts is spent on verification. Clearly, fast, thorough, and automatic verification tools which can help designers to find bugs are highly needed.

To meet these above requirements, formal methods are a good ideal candidate. They prove or disprove the validity of an implementation with respect to a certain specification using mathematical methods. By using such methods, decision procedures can be developed to handle practical circuits.  Such an approach has proved to be a great success in the EDA industry.

SZICC will invite Dr. Feng to take a speech. The speech topic is Formal Verification in IC Design.This talk mainly focuses on formal verification methods such as theorem proving, model checking, and equivalence checking. Techniques, such as  BDD, SAT, and symbolic checking model checking are also included in this talk.  

 

 

The speech time:  2005 / 1 / 22   AM 9:30-11:00

The speech place:  SIPIS  Phase II   E301 EDA training room

 

 

You are welcome!

 

 

BIOGRAPHY:

 

Xiushan Feng is a PhD student at the Department of Compute Science, University of British Columbia, Canada. He received his Master degrees of Computer Science from Institute of Technology of Computing, Chinese Academy of Sciences(2000) and University of British Columbia separately(2002). His PhD thesis will focus on Automatic Formal Verification for High-Level Model vs. Low level Implementation. He is expected to finish his PhD in UBC in 1 or 2 more years.

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